In the production of integrated circuits, it is often necessary to form openings, termed "windows" (also termed "contacts" or "vias") in one or more dielectric layers so that electrical contact may be made to underlying regions or conductors. After a window is opened, a conductive material is deposited within the window. Conductive material may also be deposited over the dielectric. The conductive layer is then lithographically patterned to form electrical conductors, often termed "runners." As integrated circuit dimensions have shrunk to below about 1 .mu.m, it has become increasingly common to planarize the dielectric layer prior to forming the windows. The planarization process yields a flatter dielectric surface for subsequent lithographic operations which may be performed to pattern the dielectric or the subsequently-formed conductive layers. In other words, a planar surface reduces the depth of field requirements for the optical system used to expose the resist layer that defines the pattern. In addition, planarization of the first dielectric layer (i.e., the one adjacent the gate and source/drain regions) facilitates the patterning of subsequent dielectric and conductive layers in so-called multi-level metal processes.
Various techniques have been developed to planarize dielectric layers. One technique, referred to as a "resist etchback," involves depositing a resist material on the surface to be planarized. Since the resist is a liquid, its top surface assumes a flat profile regardless of underlying irregularities. A plasma etch (e.g., reactive ion etch) of the hardened resist and the underlying dielectric causes the flat surface of the resist to be transferred into the underlying dielectric since the etch rate of the resist is chosen to be similar to that of the dielectric. In another technique, a mechanical wafer polisher is used to planarize the surface of the dielectric.
Unfortunately, planarization, though desirable for the reasons mentioned above, presents certain problems in subsequent processing. After a dielectric layer has been planarized, it is necessary, as mentioned before, to open windows by etching the dielectric. Since the thickness of the planarized dielectric varies with respect to the underlying topographic features, the window etching procedure may overetch and damage certain of these underlying topographic features. For example, in a typical FET window etching process, gate runners which extend over field oxides may be damaged by etching processes which are designed to open windows to source and drain regions as well as gate runners.